1. Field of the Invention
This invention relates generally to integrated semiconductor circuits and, more particularly, to comparison circuits which compare serial data signals. The invention describes a method for reducing the number of transistor elements implementing the comparison circuits.
2. Description of the Related Art
In the implementation of integrated circuits wherein a comparison of serial data signals is required, the comparison components are typically implemented as exclusive OR logic gates, exclusive NOR logic gates, AND logic gates, OR logic gates, etc. In most applications, the number of transistors required to implement each of these basic components provides an semiconductor element overhead or burden for the circuit design layout. In the circuit implementations that require comparison between serial data signals, such as in counters, adders, and parity checkers, registers are needed for storing data. Initialization circuits are required in addition to the basic gates or components performing the comparison operation. Any effort to reduce the number of transistor elements in the integrated circuit must address the problem of the number of transistors required to implement the comparison gates and the associated registers.
Referring to prior art FIG. 1, a typical comparison circuit is shown. The circuit includes a pass gate 11 to which a NEW DATA signal is applied. The NEW DATA signal and a PCNT signal are applied to the initialization circuit 14. A CLK signal is applied to register 13 and to pass gate 11. An output signal from pass gate 11 and an output signal B(T-1) is applied to comparison gate 12. An output signal from the initialization circuit 14 is applied to register 13 and is the circuit output signal B(T). In operation, the comparison circuit compares a signal B(T-1), derived during the previous clock cycle, with a NEW DATA signal to provide the current output signal B(T). The initialization circuit provides that on the first comparison operation, when no B(T-1) signal is available, the NEW DATA signal is stored in the register.
Referring to prior art FIG. 2, the circuit shown in FIG. 1 has the comparison circuit 12 specified as an exclusive OR gate 22. Both a B(T-1) and a B(T-1).sub.-- {i.e., the complement of the B(T-1) signal} are applied to the exclusive OR gate 22 in this implementation.
Referring to prior art FIG. 3, an implementation of the circuits associated with the exclusive OR gate 22 is shown. With respect to the register 13, the CLK signal is applied to an input terminal of inverting amplifier 131, to a gate terminal of a n-channel field effect transistor 136, to a p-channel control terminal of passgate transistor 134, and to a p-channel control terminal of passgate transistor 137. The output terminal of inverting amplifier provides a CLK.sub.-- signal to pass gate 11 and is coupled to an n-channel control terminal of passgate transistor 134 and to an n-channel terminal to passgate transistor 137. A drain terminal of transistor 136 is coupled to a first signal terminal of passgate 134 and to an input terminal of inverting amplifier 133. An output terminal of inverting amplifier 133 is coupled to an input terminal of inverting amplifier 132 and provides a B(T-1) signal to the exclusive OR gate 22. The output terminal of inverting amplifier is coupled to a source terminal of transistor 136 and provides the B(T-1).sub.-- signal to the exclusive OR gate 22. The B(T) signal is applied to an input terminal of inverting amplifier 138 and to a first signal terminal of passgate transistor 137. An output terminal of inverting amplifier 138 is coupled to an input terminal of inverting amplifier 135 and to second signal terminal of passgate transistor 134. The output terminal of inverting amplifier 135 is coupled to a second signal terminal of passgate 137. With respect to the pass gate 11, a NEW DATA signal is applied to a first source-drain terminal of p-channel field effect transistor 111. The CLK.sub.-- signal from register 13 is coupled to a gate terminal of transistor 111 and to a gate terminal of n-channel field effect transistor 112. The second source drain terminal of transistor 111 is coupled through source drain terminal of transistor 112 to the ground potential and provides an A signal to the exclusive OR gate 22. With respect to the initialization circuit 14, the output signal of exclusive OR gate 22 is applied to a first signal terminal of passgate transistor 141. A PCNT signal is applied to a p-channel control terminal of passgate transistor 142, to an input terminal of inverting amplifier 143 and to an n-channel control terminal of passgate transistor 141. The output terminal of inverting amplifier 143 is coupled to an n-channel control terminal of passgate transistor 142 and to a p-channel control terminal of passgate transistor 141. A NEW DATA signal is applied to a first signal terminal of pass gate transistor 142. The second signal terminal of passgate transistor 141 and a second signal terminal of passgate transistor 142 provide the B(T) signal.
Because increased complexity and miniaturization has resulted in competition for space in an integrated circuit, a need has been felt for apparatus and an associated technique for reducing the number of implementing transistors in the comparison components and associated circuits.